During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes, a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. Thereafter, the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
The etching of dielectrics may be advantageously accomplished in a dual-frequency confined, (DFC) dielectric etch system. One such is Lam® Research model Exelan HP™ or an HPT™, which is basically the same as HP with a Turbo Pump attached to the chamber, available from Lam® Research Corporation, Fremont Calif. The Exelan HP™ system provides an extremely comprehensive dielectric etch portfolio in one system. Processes include contacts and vias, bi-level contacts, borderless contacts, nitride and oxide spacers, passivation, and dual damascene etch processes.
In semiconductor-based device (e.g., integrated circuits or flat panel displays) manufacturing, dual damascene structures may be used in conjunction with copper conductor material to reduce the RC delays associated with signal propagation in aluminum-based materials used in previous generation technologies. In dual damascene, instead of etching the conductor material, vias, and trenches may be etched into the dielectric material and filled with copper.
To facilitate discussion, FIG. 1A is a cross-sectional view of a stack 100 on a wafer 110 used in the dual damascene process of the prior art. A contact 104 may be placed in a dielectric layer 108 over a wafer 110. A barrier layer 112, which may be of silicon nitride or silicon carbide, may be placed over the contact 104 to prevent the copper diffusion. A via level silicon oxide dielectric layer 116 may be placed over the barrier layer 112. A trench stop layer 120 (silicon carbide or silicon nitride) may be placed over via level dielectric 116. A trench level silicon oxide dielectric layer 124 may be placed over the trench stop layer 120. An antireflective layer (ARL) 128 may be placed over the trench dielectric layer 124. A patterned resist layer 132 may be placed over the ARL 128. The ARL 128 may be formed from silicon nitride, SiON, or other material with a high refractive index and high extinction coefficient.
FIG. 2 is a high level flow chart of a process used in the prior art to form the stack 100 into a dual damascene structure. The stack 100 may be subjected to an etch, which etches a via 140 down to the barrier layer 112 (step 204). The etching of the via 140 may form a crust 144, which forms sidewalls. The crust 144 and resist 132 may be removed and subsequently repatterned with a new resist layer 160, which is patterned to form a trench (step 208), as shown in FIG. 1C. The stack may be subjected to an etch, which etches a trench 164 down to the intermediate trench etch stop layer 120 (step 212), as shown in FIG. 1D. The etching of the trench 164 may cause part of the via level dielectric layer 116 to facet 172. This faceting may be considered as damage to the dual damascene structure. The intermediate trench etch stop layer 120 may be used to reduce faceting. The etching of the trench 164 may also form a new crust 168, which forms sidewalls. The resist layer 160 and crust may then be stripped (step 216). The stack 100 may then be subjected to a barrier layer etch (step 220), which opens the via 140 to the copper contact 104, to provide the structure shown in FIG. 1E. A metal barrier layer 174 may be deposited over the copper contact (step 224), as shown in FIG. 1F. A copper seed layer 176 may then be used to coat the interior of the via and trench. Electroplating may be used to fill the trench and via with copper 178, which is polished down to the trench dielectric layer 124. The copper 178 may be used as a copper connect for the next level, so the process is repeated creating multiple levels of copper connects and dielectric layers.
Although the intermediate trench etch stop layer may be used to reduce faceting, providing and etching the intermediate trench etch stop layer requires additional processing steps, which increases processing time and costs.
In addition, integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, k, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO2 may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO2, which materials are suitable for use in forming the dielectric layers in integrated circuits. A number of promising materials, which are sometimes referred to as “low-k materials”, have been developed. In the specification and claims, low-k materials are defined as materials with a dielectric constant k that is less than 4. Fluorosilicate glass is one example of a low-k dielectric, which has a dielectric constant of about 3.7. This composes an about 7–9% fluorine doped into SiO2.
Another interesting class of low-k materials is compounds including organosilicate glass, or OSG. By way of example, but not limitation, such organosilicate dielectrics include CORAL™ from Novellus of San Jose, Calif.; Black Diamond™ from Applied Materials of Santa Clara, Calif.; Aurora™ available from ASM International N.V., The Netherlands; Sumika Film® available from Sumitomo Chemical America, Inc., Santa Clara, Calif., and HOSP™ from Allied Signal of Morristown, N.J. Organosilicate glass materials have carbon and hydrogen atoms incorporated into the silicon dioxide lattice which lowers the density, and hence the dielectric constant of the material. A dielectric constant for such films is typically <3.0.
To facilitate discussion, FIG. 3A is a cross-sectional view of part of a wafer in the production of a damascene structure without a trench stop layer and using a low-k dielectric. A contact 304 may be placed in a low-k dielectric layer 308 over a wafer 310. A second contact 306 may also be in the low-k dielectric layer 308. A dielectric barrier layer 312, typically, but not limited to, silicon nitride or silicon carbide, may be placed over the contact 304 to prevent copper diffusion. A low-k dielectric layer 320 may be placed over the barrier layer 312. An antireflective layer (ARL) 328 may be placed over the low-k dielectric layer 320. A patterned resist layer 332 may be placed over the ARL 328. The patterned resist layer 332 is patterned to provide a via 340, which is etched into the low-k dielectric layer 320. The resist layer 332 is removed and a second patterned resist layer 360 is placed over the ARL 328. The second resist layer 360 is patterned to provide a trench 364, which is etched into the low-k dielectric layer 320.
Because of the absence of the intermediate trench etch stop layer and the use of a low-k dielectric, faceting 372 in this example may be increased. Such faceting may cause the copper, which would be used to fill in the via and trench, to be too close to the second contact 306. This may also increase the dimension of the bottom of the via.
To facilitate understanding, FIG. 4A is a cross-sectional view of part of a wafer in the production of a damascene structure without a trench stop layer and using a low-k dielectric. A first contact 404 and a second contact 406 may be placed in a low-k dielectric layer 408 over a wafer 410. A dielectric barrier layer 412, typically, but not limited to silicon nitride or silicon carbide, may be placed over the first and second contacts 404, 406 to prevent the copper diffusion. A low-k dielectric layer 420 may be placed over the barrier layer 412. First 440 and second 444 vias may be etched into the low-k dielectric layer 420. A bottom antireflective coating (BARC) layer 428 may be spun over the low-k dielectric layer 420. Such a spun on BARC tends to at least partially fill the vias 440, 444 and form sidewalls in the vias. Generally, thinner vias are filled with BARC to a higher depth than wider vias are filled. Also, more spread apart vias may be filled higher than more closely packed vias. As a result, it may be difficult to have the vias filled to a uniform height.
FIG. 4B is a cross-sectional view of part of the wafer after trenches 448, 452 have been etched. The presence of BARC in the vias creates fences 456, 460 and, in addition, faceting 462, 464. The amount of faceting and the size of the fences are dependent on the height of the BARC. Therefore, non-uniform BARC height may cause non-uniform faceting and fences. The fences may be a stress location, which may cause electro-migration, voids and other failures, which may diminish the reliability of the resulting semiconductor devices.